B.E. (CSE), NIT Rourkela, 1994.
MTech (CSE), IIT Bombay, 1996.
PhD. (CSE), IIT Kharagpur, 2008.
NIT Durgapur, Department of Computer Science and Engineering, June 1998 -- present.
NIT Rourkela, Department of Computer Science and Engineering, 1996 - 1998.
VLSI Design Automation and Testing.
FPGA based Embedded System design.
Hardware Security. Boolean Satisfiability. Formal Methods.
Title | Investigator | Co-investigator | Sponsered Agency | Duration | Status |
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Subjects Taught Algorithm Analysis and Design
Formal Languages and Automata Theory
Operating Systems
Distributed Systems
Computer Networks
Testing and Verification of VLSI systems
Algorithms for VLSI Physical Design
Compiler Design
Digital Logic
Computer Organisation
Object Oriented Programming
Machine Learning
Sl.No. | Title | Name of the PI | Name of the CoPIs | Funding Agency | Amount (Rs.) | Project Type | Project Status | Date of Initiation | Date of Completion |
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1 | Secure Architecture for FPGA based IoT Applications with enhanced physically unclonable function | Dr. Bibhash Sen | Dr. Suchismita Roy | DST-SERB (Core Research/ EMR scheme) | 1,624,000 | Sponsored | Ongoing | 2018 | |
2 | ADKit: Smartphone Based Artificial Intelligence Enabled Portable Low-cost Anemia Detection Kit based on Observation of Nail and Palm Pallor | Dr. Mamata Dalui | Dr. Suchismita Roy et. al. | Meity, Govt of India | 2,894,000 | Sponsored | Ongoing | 2018 | |
3 | Design of light weight and cost effective PUF-Enabled secure architecture for authentication and FPGA based application | Dr. Bibhash Sen | Dr. Suchismita Roy (Co-PI) | WB-DSTWB-DST | 800,000 | Sponsored | Ongoing | 2018 | |
4 | Routing and Routability Checking in Island Style FPGA Architechtures | Dr. Suchismita Roy | RIG-I, NIT Durgapur | 850,000 | Sponsored | Completed | 2014 | 2017 | |
5 | DST-FIST | Dr. Suchismita Roy | MHRD, Govt. of India | 5,100,000 | Sponsored | Completed | 2010 | 2015 | |
6 | Neurocomputing and Cognitive Intelligence - Developing a model for Analysing the Learning Disabilities of Dyslexic Child | Dr. Bibhash Sen | Dr. Suvrojit Das Prof. Suchismita Roy Prof. Anupam Basu | Meity, Govt of India | 4,950,000 | Sponsored | Ongoing |
Sl.No. | Title | Name of the PI | Name of the CoPIs | Funding Agency | Amount (Rs.) | Project Type | Project Status | Date of Initiation | Date of Completion |
---|---|---|---|---|---|---|---|---|---|
1 | Secure Architecture for FPGA based IoT Applications with enhanced physically unclonable function | Dr. Bibhash Sen | Dr. Suchismita Roy | DST-SERB (Core Research/ EMR scheme) | 1,624,000 | Sponsored | Ongoing | 2018 | |
2 | ADKit: Smartphone Based Artificial Intelligence Enabled Portable Low-cost Anemia Detection Kit based on Observation of Nail and Palm Pallor | Dr. Mamata Dalui | Dr. Suchismita Roy et. al. | Meity, Govt of India | 2,894,000 | Sponsored | Ongoing | 2018 | |
3 | Design of light weight and cost effective PUF-Enabled secure architecture for authentication and FPGA based application | Dr. Bibhash Sen | Dr. Suchismita Roy (Co-PI) | WB-DSTWB-DST | 800,000 | Sponsored | Ongoing | 2018 | |
4 | Routing and Routability Checking in Island Style FPGA Architechtures | Dr. Suchismita Roy | RIG-I, NIT Durgapur | 850,000 | Sponsored | Completed | 2014 | 2017 | |
5 | DST-FIST | Dr. Suchismita Roy | MHRD, Govt. of India | 5,100,000 | Sponsored | Completed | 2010 | 2015 | |
6 | Neurocomputing and Cognitive Intelligence - Developing a model for Analysing the Learning Disabilities of Dyslexic Child | Dr. Bibhash Sen | Dr. Suvrojit Das Prof. Suchismita Roy Prof. Anupam Basu | Meity, Govt of India | 4,950,000 | Sponsored | Ongoing |
Sl.No. | Title | Name of the PI | Name of the CoPIs | Funding Agency | Amount (Rs.) | Project Type | Project Status | Date of Initiation | Date of Completion |
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ID | Details | Year |
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2023 | 1. Towards the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen ACM Journal on Emerging Technologies in Computing Systems (JETC) SCI ACM | 2023 |
2023 | 2. Smartphone-based non-invasive haemoglobin level estimation by analysing nail pallor Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu Elsevier Biomedical Signal Processing and Control Vol. 85 SCI https://doi.org/10.1016/j.bspc.2023.104959 Elsevier | 2023 |
2023 | 3. Non-invasive Anaemia Detection by Examining Palm Pallor: A Smartphone-based Approach Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu Elsevier Biomedical Signal Processing and Control 79 (1) SCI https://doi.org/10.1016/j.bspc.2022.104045 Elsevier | 2023 |
2022 | 4. Hardware Trojan Detection using Transition Probability with Minimal Test Vectors Anindan Mondol, Bibhash Sen, Suchismita Roy ACM Transactions on Embedded Computing Systems 22(1), Pages 1 - 21 SCI https://doi.org/10.1145/3545000 ACM | 2022 |
2022 | 5. Congestion-aware Rectilinear Steiner Tree Construction using PB-SAT Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee Journal of Circuits, Systems and Computers Accepted for Publication SCIE World Scientific | 2022 |
2022 | 6. Power Aware Floorplanning in Multiple Supply Voltage Domain Suchandra Bannerjee, Suchismita Roy Journal of Circuit Theory and Applications (CTA) Vol : 50(2), pages: 382-393 SCIE Wiley International | 2022 |
2021 | 7. An Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Method using PB-SAT Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee IETE Journal of Research Accepted for Publication SCIE Taylor and Francis | 2021 |
2021 | 8. Hardware Trojan Free Netlist Identification : A Clustering Approach Anindan Mondol, Mahbub Hasan Mahalat, Rajesh Jaiswal, Bibhash Sen, Suchismita Roy Journal of Electronic Testing: Theory and Applications (JETTA) Vol: 37(3), pages: 317-328 SCIE Springer US | 2021 |
2021 | 9. Thermal-Driven Floorplanning for Fixed Outline Layouts Suchandra Bannerjee, Suchismita Roy Journal of Circuits, Systems and Computers Vol: 30(5), pages 2150079(1-19) SCIE DOI: 10.1142/S0218126621500791 (2021) World Scientific | 2021 |
2020 | 10. Efficient Algorithm forComputing the triangle maximising the length of its smallest side inside a convex polygon Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhash C. Nandy, Suchismita Roy International Journal of Foundations of Computer Science Vol: 31(4), pages: 421-443 SCI World Scientific | 2020 |
2020 | 11. Rectilinear Steiner Tree Construction Techniques using PB-SAT based Methodology Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee World Scientific Journal of Circuits, Systems and Computers Vol: 29(4), pages: 2050057:1-2050057:22 SCI https://doi.org/10.1142/S0218126620500577 World Scientific | 2020 |
2019 | 12. Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy Theoretical Computer Science Vol. 769, pages 63-74 SCI Elseviers | 2019 |
2019 | 13. Corrigendum to “Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares" Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhash C. Nandy, Suchismita Roy Theoretical Computer Science Vol: 806, pages: 632-640 SCI Elseviers | 2019 |
2019 | 14. An Integrated Framework for Application Independent Testing of FPGA Interconnects Shukla Banik, Suchismita Roy, Bibhash Sen Journal of Electronic Testing : Theory and Applications Vol. 35, pages729–740 SCI Springer | 2019 |
2019 | 15. Application Dependent Testing of FPGA Interconnect Networks Shukla Banik, Suchismita Roy, Bibhash Sen IEEE Transactions on Very Large Scale Integrated Systems (TVLSI) Vol. 27(10), pages 2296-2304 SCI IEEE | 2019 |
2018 | 16. A SAT-based Methodology for Effective Clock gating for Power Minimization Khushbu Chandrakar, Suchismita Roy World Scientific Journal of Circuits, Systems and Computers Vol. 28, No. 01, 1950011 SCI World Scientific | 2018 |
2016 | 17. Nearly-2-SAT Solutions for Segmented Channel Routing Shyamapada Mukherjee, Suchismita Roy IEEE Transactions on Computer Aided design of Integrated Circuits (TCAD) Vol. 35 (1), pages 128-140 SCI IEEE | 2016 |
2016 | 18. Via –aware Dogleg Router using Boolean Satisfiability Shyamapada Mukherjee, Suchismita Roy World Scientific Journal of Circuits, Systems and Computers Vol. 26, No. 4, pages 1750064-1 to 24 SCI World Scientific | 2016 |
2015 | 19. SAT Based Solutions for Detailed Routing of Island Style FPGA Architectures Shyamapada Mukherjee, Suchismita Roy Elseviers Microelectronics Journal (MEJ) Vol. 46(8), pages 706-715 SCI Elseviers | 2015 |
2012 | 20. SAT based Timing Analysis for Fixed and Rise/Fall Gate Delay Models Suchismita Roy, P.P.Chakrabarti, Pallab Dasgupta Integration : The VLSI Journal Vol. 45, Issue 4, pages 357-364 SCI Elseviers | 2012 |
2010 | 21. Bounded Delay Timing Analysis and Power Estimation Suchismita Roy, P.P.Chakrabarti, Pallab Dasgupta. Elseviers Microelectronics Journal (MEJ) Vol. 41, issue 5, pages 317-324 SCI Elseviers | 2010 |
2008 | 22. Satisfiability Models for Maximum Transition Power. Suchismita Roy, P.P.Chakrabarti, Pallab Dasgupta. IEEE Transactions on Very Large Scale Integrated Systems (TVLSI) Vol. 16, no. 8, pages 941-951 SCI IEEE | 2008 |
2007 | 23. Event Propagation for Accurate Circuit Delay Calculation using SAT. Suchismita Roy, P.P.Chakrabarti, Pallab Dasgupta ACM Transactions on Design Automation of Electronic Systems (TODAES) Vol. 12, no. 3, pages 1-23 SCI ACM | 2007 |
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Head of the Department 2009 -2011 and 2013 -2015
Dean (Faculty Welfare) at present.
Mobile : +91-9434788122
Email : suchismita.roy@cse.nitdgp.ac.in
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