Electronics and Communication Engineering

Faculty Details

Ashis Kumar Mal Professor(ECE)
CV
Joined the Institute in 25th May 2007
akmal[dot]ece[at]nitdgp[dot]ac[dot]in
Publication

36

Publications

1

Sponsored Projects

0

Consultancy Projects
Education

12

Doctoral Students

0

UG Students

26

PG Dissertation
Education
PhD IIT Kharagpur , India 2009
M.Tech IIT Kanpur , India 1994
B.Tech BE College (CU, Kolkata), India 1987

Internship Opening: We are inviting applications for internship (May-June: 2025), in Analog & Mixed Signal VLSI, Digital Design, Embedded System and Hardware Design  (any area) using Raspberry/Arduino. 
Who Can Apply : Students in Prefinal-year ECE, Second-year ECE (GPA>8.0/10), preferably from Durgapur and adjoining areas. Limited hostel facility may be provided based on availibilty of rooms. Interested candidates may apply through this link with CV indicating specificic area(s) of Interest. Limited stipends may be available for NITD/CFTI/SFTI students.

Teaching: In the coming Semester (2024-25, Even) we will offer an open-elective paper focussed on VLSI-Chip Fabrication. The Title of the paper/subject is "Fundamentals of Micro, Nano Fabrication and Packaging (XEO852)" Objective of this subject to train manpower ( ISWDP) required for upcoming IC Fabrication Industry which is one of the goals of India Semiconductor Mission with partners like IISc, LAM Research supported by MeitY. A tentative outline of the course is here.

akmal [AT] ece [DOT] nitdgp [DOT] ac [DOT] IN

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My Teachers: Sh. Kanai Lal Samui, Prof. Haranath Kar, Prof. Anindya Sundar Dhar, Prof. Pradip Mandal 

Work Experiences

More than 30 years (1992 - )  in Teaching & Research.

Research Interest
Projects
Title Investigator Co-investigator Sponsered Agency Duration Status

Chips to Startup (C2S) : Chief-Investigator : Dr. Hemanta Mondal, Chief-Investigator(Co-CI): Dr. Aniruddha Chandra, MeitY, 2021- , Ongoing.. 

Special Manpower Development Project for Chips to System Design (SMDP-C2SD), Sponsored by Ministry of Electronics & Information Technolgy (MeitY), Govt. of India (2014 - 2021). Co-Investigator(CI) Prof. Rajat Mahapatra

Special Manpower Development Project : Phase II(SMDP-II),  MeitY, (2006-2014), Completed

For more information, visit our SMDP-C2SD webpage.

Layout of Analog Front End (AFE)

         Ongoing

 

Teachings
ID Subject Name Subject Code Semester Degree Download Key
999997 Analog IC Design ECE712 7th UG
999996 Basic ELectronics ECC-01 1st UG
999974 Mixed Signal IC Design EC9028 2022-23(Even) PG
999972 Microelectronics ECC405 Sem-4(2024-25) UG
999971 Fundamentals of Micro, Nano Fabrication and Packaging XEO849 Sem-8(2024-25) UG
Subject Name Subject Code Semester Degree Download Key
Computer Aided Laboratory (LTSPICE) ECS751 7 UG
Analog ELectronics Lab Manual (OpAmp) EC5XX 5 UG
 
Digital Lab Manual EC 452/1062 4 UG
 
Digital Circuits & Systems ECS452 4 UG
 
FPGA Lab Manual EC206X 3 PG
 
Analog IC Design EC1012 1 PG
 
Semi-Log Graph Paper EC000 0 UG
 
Digital Lab Manual (B) ECS452B 4 UG
 
Mixed Signal IC Design(Course Plan) EC9041 2 PG
 
Network Analysis & Synthesis ECC301 3 UG
 
Analog VLSI Design EC724 7 UG
 
Microwave Lab Manual ECS552A 5 UG
 
LTSpiceIV_Introduction EC6XX 2 UG
 
Summer Internship ECS754 7 UG
 
Analog VLSI Design (Slides) EC724 7 UG
 
Lab Manual for AC Circuits EC2XY 1 UG
 
Electronic System Design(Ti-ASLK) ECS751 7 UG
 
Communication Lab Manual ECS451 5 UG
 
Network Analysis & Synthesis Lab ECS351 3 UG
 
Lab Manual for DC Circuits EC1XY 1 UG
 
Analog ELectronics Lab Manual EC3XY 3 UG
 
Two Port Network EC000 0 UG
 
Signal analysis & Communication Lab Manual ECS303 3 UG
 
Mixed Signal IC Design(L1) EC9041 2 PG
 
Digital Communication Lab Manual ECS551 5 UG
 
Analog VLSI Design(Lab. Assignment) EC724 7 UG
 
LTSpiceIV_Manual ECS751 7 UG
 
       
 

Teaching:

2024-25 (Even Sem) : Microelectronic Circuits (ECC404, UG); Fund. of Micro, Nano Fabrication & Packaging (XEO852, UG)

2024-25 (Even Sem) : Microelectronic Circuits (ECC404, UG); Fund. of Micro, Nano Fabrication & Packaging (XEO852, UG)

UG Students

Data Not Found!

PG Students

Data Not Found!

Doctoral Students

Sanjukta Mandal

Sanjukta Mandal

Assistant Professor in Techno India University, Kolkata
Studies on designing On-Chip Antennas in Silicon IC for Short RangeCommunication.
Sanjukta Mandal

Sanjukta Mandal

Assistant Professor in Techno India University, Kolkata
Studies on designing On-Chip Antennas in Silicon IC for Short RangeCommunication.
Amrita Mukherjee

Amrita Mukherjee

Ongoing...
Improving Spectral Efficiency and Performance of Wireless Networks Using Non-Orthogonal Multiple Access and Full-Duplex Signaling.
Enhancing Spectrum Efficiency and Performance of Wireless Networks using the Principles of Underlay Cognitive Radio, Full-Duplex Technology and Non-Orthogonal Multiple Access
Amrita Mukherjee

Amrita Mukherjee

Ongoing...
Improving Spectral Efficiency and Performance of Wireless Networks Using Non-Orthogonal Multiple Access and Full-Duplex Signaling.
Enhancing Spectrum Efficiency and Performance of Wireless Networks using the Principles of Underlay Cognitive Radio, Full-Duplex Technology and Non-Orthogonal Multiple Access
Satyam Shivam Sundram

Satyam Shivam Sundram

in Service at NIT Patna
Microelectronics & VLSI, FDDA Design, Neuromorphic Circuits, SIP Modelling, SC/SI Filter Circuits.
Low-Power Analog CMOS Circuits.
Satyam Shivam Sundram

Satyam Shivam Sundram

in Service at NIT Patna
Microelectronics & VLSI, FDDA Design, Neuromorphic Circuits, SIP Modelling, SC/SI Filter Circuits.
Low-Power Analog CMOS Circuits.
Anu Samanta

Anu Samanta

Ongoing
Digital VLSI Design for DSP[Currently working as Assistant Professor, ECE Department, NSHM Durgapur]
Approximate computing-based reconfigurable VLSI architecture of the DSP algorithm for the edge computing system design(Tentative)
Anu Samanta

Anu Samanta

Ongoing
Digital VLSI Design for DSP[Currently working as Assistant Professor, ECE Department, NSHM Durgapur]
Approximate computing-based reconfigurable VLSI architecture of the DSP algorithm for the edge computing system design(Tentative)
Dr. Sumalya Ghosh

Dr. Sumalya Ghosh

Sankalp Semiconductors Kolkata
Optimal Design of CMOS Analog and RF Circuits Using Evolutionary Techniques
Dr. Sumalya Ghosh

Dr. Sumalya Ghosh

Sankalp Semiconductors Kolkata
Optimal Design of CMOS Analog and RF Circuits Using Evolutionary Techniques
Dr. Rishi Todani

Dr. Rishi Todani

CEO, Printking
Analog & Mixed-Signal VLSI Design, Design, and Implementation of Analog Frontend Amplifier (AFE) for Seismic System. Worked as Project Faculty (ECE) in SMDP-C2SD, MeitY, GoI Project at NIT Durgapur. 
Design of Low Power, Area Efficient Switched-Capacitor Circuits in CMOS Technology 
Dr. Rishi Todani

Dr. Rishi Todani

CEO, Printking
Analog & Mixed-Signal VLSI Design, Design, and Implementation of Analog Frontend Amplifier (AFE) for Seismic System. Worked as Project Faculty (ECE) in SMDP-C2SD, MeitY, GoI Project at NIT Durgapur. 
Design of Low Power, Area Efficient Switched-Capacitor Circuits in CMOS Technology 
Dr. Joydeep Howlader

Dr. Joydeep Howlader

Assistant Professor, Department of Computer Science and Engineering, National Institute of Technology Durgapur
Design and Analysis of Receipt-Free Sealed-Bid Auction
Dr. Joydeep Howlader

Dr. Joydeep Howlader

Assistant Professor, Department of Computer Science and Engineering, National Institute of Technology Durgapur
Design and Analysis of Receipt-Free Sealed-Bid Auction
Prof. Subhrabrata Choudhury

Prof. Subhrabrata Choudhury

Professor, Department of Computer Science and Engineering, National Institute of Technology Durgapur
Design of Efficient Protocols and Algorithms for Optical Burst Switched Network
Prof. Subhrabrata Choudhury

Prof. Subhrabrata Choudhury

Professor, Department of Computer Science and Engineering, National Institute of Technology Durgapur
Design of Efficient Protocols and Algorithms for Optical Burst Switched Network
Dr. RSSM Ramakrishna

Dr. RSSM Ramakrishna

Analog Engineer at Intel Corporation
CMOS Time-Domain Temperature Sensor Circuits using Σ∆ Time-to-Digital Converters
Dr. RSSM Ramakrishna

Dr. RSSM Ramakrishna

Analog Engineer at Intel Corporation
CMOS Time-Domain Temperature Sensor Circuits using Σ∆ Time-to-Digital Converters
Dr. Madhusmita Panda

Dr. Madhusmita Panda

Assitant Professor ITER, SOA, Bhubaneswar, Odisha 751030
Currently serving as Assistant Professor at ITER, Siksha 'O' Anusandhan, Bhubaneswar, Odisha
Ultra Low power VCO design for PLL.
Dr. Madhusmita Panda

Dr. Madhusmita Panda

Assitant Professor ITER, SOA, Bhubaneswar, Odisha 751030
Currently serving as Assistant Professor at ITER, Siksha 'O' Anusandhan, Bhubaneswar, Odisha
Ultra Low power VCO design for PLL.
Dr. Rajib Kar

Dr. Rajib Kar

Associate Professor, NIT Durgapur
Modelling of High Speed Interconnect in VLSI Design
Dr. Rajib Kar

Dr. Rajib Kar

Associate Professor, NIT Durgapur
Modelling of High Speed Interconnect in VLSI Design
Dr. Biswajit Ghosh

Dr. Biswajit Ghosh

Assistant Professor, UEM Kolkata
Research Area: Energy Efficient Relay Placement for WSN.
Dr. Biswajit Ghosh

Dr. Biswajit Ghosh

Assistant Professor, UEM Kolkata
Research Area: Energy Efficient Relay Placement for WSN.

Projects

Sl.No. Title Name of the PI Name of the CoPIs Funding Agency Amount (Rs.) Project Type Project Status Date of Initiation Date of Completion
1 Special Manpower Development Project for Chips to System Design (SMDP-C2SD) Ashis Kumar Mal Prof. Rajat Mahaptra, Co-Chief Investigator Ministry of Electronics & Information Technolgy (MeitY), Govt. of India (2014 - 2021) Sponsored Completed 2014-12-15 2021-07-31

Projects

Sl.No. Title Name of the PI Name of the CoPIs Funding Agency Amount (Rs.) Project Type Project Status Date of Initiation Date of Completion
1 Special Manpower Development Project for Chips to System Design (SMDP-C2SD) Ashis Kumar Mal Prof. Rajat Mahaptra, Co-Chief Investigator Ministry of Electronics & Information Technolgy (MeitY), Govt. of India (2014 - 2021) Sponsored Completed 2014-12-15 2021-07-31

Projects

Sl.No. Title Name of the PI Name of the CoPIs Funding Agency Amount (Rs.) Project Type Project Status Date of Initiation Date of Completion
Indexing

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Scopus h-index

Journals

ID Details Year
2023 1. An energy-efficient voice activity detector using reconfigurable Gaussian base normalization deep neural network.  Anu Samanta; Indranil Hatai; Ashis Kumar Mal Multimed Tools Appl (2023) Page(s): 1-22 SCI https://doi.org/10.1007/s11042-023-14699-1 Springer https://rdcu.be/dcdS5 2023
2023 2. Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA Amrita Mukherjee; Pratik Chakraborty; Shankar Prakriya; Ashis Kumar Mal IEEE Transactions on Wireless Communications Vol. 22, (5), Page(s): 3161-3179 SCI 10.1109/TWC.2022.3216332 https://ieeexplore.ieee.org/document/9932279/ 2023
2022 3. A UWB Dual Band-Notched on-Chip Antenna and Its Equivalent Circuit Model Sanjukta Mandal, Sujit Kumar Mandal, Ashis Kumar Mal; Rajat Mahapatra Progress In Electromagnetics, Research B Vol. 97, Page(s): 19-35 SCI/SCOPUS 10.2528/PIERB22072602 https://www.jpier.org/issues/volume.html?paper=22072602 2022
2022 4. A 24 GHz Circularly Polarized On-chip Antenna for Short-Range Communication Application Sanjukta Mandal, Sujit Kumar Mandal, Ashis Kumar Mal; Rajat Mahapatra; P. R. T. Naidu Scientia Iranica, Transaction D: Computer Science & Engineering and Electrical Engineering SCI/SCOPUS 10.24200/SCI.2022.57325.5202 2022
2022 5. Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection  Amrita Mukherjee; Pratik Chakraborty; Shankar Prakriya; Ashis Kumar Mal IEEE Transactions on Signal and Information Processing over Networks Vol.8, Page(s): 932-945 SCI https://ieeexplore.ieee.org/abstract/document/9956915 2022
2021 6. Design of a super-wideband on-chip antenna with improved characteristics using bulk micromachining Sanjukta Mandal; Sujit Kumar Mandal; Ashis Kumar Mal; Rajat Mahapatra Microsystem Technologies Vol. 28, Page(s): 937-946 SCI 10.1007/s00542-021-05242-z Springer https://link.springer.com/article/10.1007/s00542-021-05242-z 2021
2019 7. Symbiotic Organisms Search Algorithm for Optimal Design of CMOS Two-stage Op-amp with Nulling Resistor and Robust Bias Circuit (Accepted: In Press) IET Circuits, Devices & Systems SCI/SCOPUS 2019
2019 8. Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm. 18(2), 737-747. Journal of Computational Electronics SCI/SCOPUS 2019
2019 9. Fast and Optimized Design of a Differential VCO using Symbolic Technique and Multi-Objective Algorithms (Accepted) IET Circuits Devices & Systems SCI/SCOPUS 2019
2019 10. Time-Domain Smart Temperature Sensor using Current Starved Inverters and Switched Ring Oscillator based Time-to-Digital Converter (Accepted) Circuits, Systems, and Signal Processing, Birkhäuser Boston - Springer. SCI/SCOPUS 2019
2019 11. All MOS Noise-shaped Time-Mode Temperature Sensor. 65 (C), 74 - 80. Integration the VLSI Journal, Elsevier SCI/SCOPUS 2019
2019 12. A cost-effective system for triggering alarm to distracted drivers/ nurses Debabrata Bej, Subhajit Rakshit, Ashis Kumar Mal, Rajat Mahapatra Computers & Electrical Engineering 76 (C), 24 - 39 SCIE 10.1016/j.compeleceng.2019.03.001 Elsevier BV 2019
2019 13. CMOS time-mode smart temperature sensor using programmable temperature compensation devices and   ΔΣ  time-to-digital converter R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra Analog Integrated Circuits and Signal Processing 1-13 SCI 10.1007/s10470-019-01544-5 Springer US 2019
2019 14. A miniaturized CPW-Fed On-Chip UWB monopole antenna with Band Notch characteristic. (Accepted) International Journal of Microwave and Wireless Technology SCI/SCOPUS 2019
2018 15. Performance enhancement of a VCO using symbolic modelling and optimisation. 12(2), 196 – 202. IET Circuits, Devices & Systems SCI/SCOPUS 2018
2017 16. Optimal Location of Energy Efficient DF Relay Node in κ – μ Fading Channel. 96 (1), 669-682. Wireless Personal Communications SCI/SCOPUS 2017
2016 17. Energy efficient DF relay placement in α-μ fading channel with cooperative and non-cooperative schemes. 25 (4), 749 - 756. Radioengineering SCI/SCOPUS 2016
2015 18. Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment. 8, 3415 - 3440. SECURITY AND COMMUNICATION NETWORKS SCI/SCOPUS 2015
2014 19. Simulator based device sizing technique for operational amplifiers.13, 11-28.   WSEAS Transactions on Circuits and Systems SCI/SCOPUS 2014
2014 20. A digitally assisted telescopic amplifier with improved ICMR and programmable unity gain frequency. 13, 301-312. WSEAS Transactions on Circuits and Systems SCI/SCOPUS 2014
2012 21. Routing scheme for OBS networks. 4 (10), 799-811. IEEE/OSA Journal of Optical Communications and Networking SCI/SCOPUS 2012
2010 22. Impact of Burst Assembly Algorithms on Data Loss in OBS Networks Under Time-Correlated Traffic Input. 2 (12), 1063-1076. IEEE/OSA Journal of Optical Communications and Networking SCI/SCOPUS 2010

Conferences

ID Details Year
2021 1.Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection by Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal, in IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS-2021), pages: 296-301. Hyderabad 2021
2019 2.Design of a Compact Monopole On-chip Antenna for 24 GHz Automotive Radar Application, IEEE International Workshop on Antenna Technology (iWAT) Miami 2019
2018 3.Band frequency generation using mixed signal controlled ring — Oscillator, 2nd International Conference on Inventive Systems and Control (ICISC): 26-31. Coimbatore 2018
2017 4.Design of low noise amplifier for sensor applications,2017 Devices for Integrated Circuit (DevIC): 451-455 Kalyani 2017
2017 5.Design of a Compact UWB On-chip Antenna using Standard CMOS Technology, 3rd ISSE National Conference on Complex Engineering Systems of National Importance: Current Trends & Future Perspectives: 91 Mohali 2017
2017 6.Studies on on-chip antenna using standard CMOS technology, 2017 IEEE Conf. on Devices for Integrated Circuit(DevIC): 471-475. Kalyani 2017
2016 7.Performance analysis of parallel adders in sub-micron and deep sub-micron technologies, 2016 International Conference on Microelectronics, Computing and Communications (MicroCom): 1 - 5 Durgapur 2016
2016 8.Design of substantial delay block using voltage scaled CMOS inverter and transmission gate blend, 2016 International Conference on Microelectronics, Computing and Communications (MicroCom): 1 - 6 Durgapur 2016

Books

ID Title
Voltage-Controlled Ring Oscillator for Harmonic Frequency Generation. In: Mandal D., Kar R., Das S., Panigrahi B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi 1. Voltage-Controlled Ring Oscillator for Harmonic Frequency Generation. In: Mandal D., Kar R., Das S., Panigrahi B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi
Design of Low-Noise Amplifier with High CMRR for Sensor Application. In: Bhattacharyya S., Gandhi T., Sharma K., Dutta P. (eds) Advanced Computational and Communication Paradigms. Lecture Notes in Electrical Engineering, vol 475. Springer, Singapore (2018). 2. Design of Low-Noise Amplifier with High CMRR for Sensor Application. In: Bhattacharyya S., Gandhi T., Sharma K., Dutta P. (eds) Advanced Computational and Communication Paradigms. Lecture Notes in Electrical Engineering, vol 475. Springer, Singapore (2018).
Amplifier Design Optimization in CMOS. In: Mandal D., Kar R., Das S., Panigrahi B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi 3. Amplifier Design Optimization in CMOS. In: Mandal D., Kar R., Das S., Panigrahi B. (eds) Intelligent Computing and Applications. Advances in Intelligent Systems and Computing, vol 343. Springer, New Delhi
180-nm 20 ps Resolution 0.29 LSB Single-Shot Precision Vernier Delay Line Based Time-to-Digital Converter. In: Anguera J., Satapathy S., Bhateja V., Sunitha K. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 471. Springer, Singapore. 4. 180-nm 20 ps Resolution 0.29 LSB Single-Shot Precision Vernier Delay Line Based Time-to-Digital Converter. In: Anguera J., Satapathy S., Bhateja V., Sunitha K. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 471. Springer, Singapore.

For Publications See here.

 5.

For Publications See here.

Patents

ID Details Patent Filed Year
2021 1. A SYSTEM AND A METHOD FOR MONITORING AND RATING ALERTNESS REMOTELY 2021 Ashis Kumar Mal, Debabrata Bej  Granted 2021
Awards and Recognitions
Administrative Responsibilities
  • Head of the Department (ECE) (2018-2021)
  • Chief Investigator, SMDP-C2SD Project (MeitY, GoI), ECE Department, NIT Durgapur (2014 - 2021)
  • Chief Designer, SMDP-II Project (MeitY, GoI), ECE Department, NIT Durgapur (2007 - 2014)
  • Warden, CV Raman Hall of Residence (2008-2012)
Contact

Phone : +91-343-275-4389(O), 3389(R), 4377(ECE-Off)
Email : akmal @ ece . nitdgp . ac . in, ashis.mal @ ieee.org

Miscellaneous

Students interested to carry out Internship in Hardware-based projects are advised to send their resumes. Students completed their 6th Sem. in ECE may be considered for Summer internships in SMDP-VLSI Lab.

For more information please visit SMDP VLSI Laboratory, NIT Duragpur

Contact: akmal @ ece.nitdgp.ac.in, ashis.mal @ ieee.org

Top recruiters: Intel, Qualcomm, Apple, Samsung, STMicro, Ti, NXP

Academic Identity

Orcid Id
https://orcid.org/0000-0001-7208-4352
Scopus Id
https://www.researchgate.net/profile/Ashis-Kumar-Mal
Researcher Id
https://ieeexplore.ieee.org/author/37265587300
Google Scholar Id